|System Verilog||5-10 Years||Essential|
|UVM Methodology||5-10 Years||Essential|
For our client we are looking for a Senior ASIC Verification Engineer!
Responsibilities & Tasks
• Define and implement UVM based test environments for IPs and subsystem.
• Develop, run and debug testcases.
• Usage of uVC´s
• Development of uVC´s (if needed)
• Usage of reference models (if needed)
• Constrained random testing
• Creation of Coverage matrix
• Writing Verification Report
• Several years’ experience in verification using System Verilog and UVM
• Knowledge of Verilog/VHDL
• Knowledge of Object-Oriented Programming concepts
• Experience in developing test plans and directed/randomized test cases from scratch
• Experience in formal verification
• Experience with simulation verification tools (Mentor/Cadence)